The Xilinxⁱ Platform Studio (XPS) tool is a system-on-chipⁱ development environment for Xilinxⁱ FPGAsⁱ. This development suite allows designers to create customized system-on-chipⁱ hardware within an FPGAⁱ and develop custom programs to run on any microprocessors which might be in the hardware design.

Starting with XPS

To get started with the XPS development suite you will need to run the application by selecting the appropriate entry from the Start Menu. Once the application has loaded you will be presented with a start up wizard similar to the one on shown on the right. If you have an existing XPS project then simply select "Open a recent project". Otherwise select the base system builder wizard. This wizard will help you setup a basic system-on-chipⁱ design correctly for your FPGAⁱ. We recommend the use of this wizard over doing everything manually at is substantially eases development. For more information about the base system build please read the Base System Builder Tutorial.

Once you have either opened your existing project or finished using the base system builder you will be presented with the main XPS development window. This window contains many important sections which are accessed by clicking on the appropriate tab or button.

Bus Interface View

The first view to take notice of is the bus interface view. This view appears in the main editing section when the Bus Interface option is selected inside of the system assembly section. The bus interface view presents a list of all soft-IP cores which are in the system. Left clicking on a core allows you to change the name of the core while right clicking presents a context-sensitive menu which allows you to configure the core, view the documentation for the core, and many other things.

Additionally, in the left part of the view a graphical representation of the bus interconnect scheme is shown. This graphical view shows all of the buses in the system along with an indication of which cores are connected to those buses. Squares represent masters connected to the bus while circles represent slaves. A filled indicator means that the device listed to the left is connected to the given bus while a unfilled circle means that the peripheral is not connected to that bus.

Ports View

By selecting the Ports option in the system assembly section you can view all of the ports in your system-on-chipⁱ design. Ports are communication end points and can either be single wire connections or bus connections. By default the displayed list shows all of the soft-IP cores in the design. By clicking on the plus sign next to a core you can view all of the ports associated with that core along with many useful properties about that port. Using the ports view you can connect any two compatible ports together in your system by giving them the same net name.

It is worth noting that there are useful port filters available for use by clicking on the Connection Filters button. Doing this will present only the ports which match the given filter and can make working with large designs much easier. Additionally, new nets can be created simply by giving a port a net name which does not already exist. Net connections which go off chip, i.e. connections which go through an I/O buffer and off chip to the board peripherals, can be created using the Add External Port button.

Addresses View

Selecting the Addresses option in the system assembly section will show the memory mapped addresses view. This view shows all of the valid memory addresses in the system along with the soft-IP core which is associated with those memory addresses. Most soft-IP core peripherals have only one memory mapped address range. This address range defines where that peripheral appears at in the memory space. For example, consider the following memory map:

• 0x00000000 - 0x00001FFF : BRAMⁱ Memory
• 0x40000000 - 0x4000FFFF : LEDⁱ GPIOⁱ
• 0x41000000 - 0x4100FFFF : RS232 UART

Any microprocessor connected to the same bus as the given peripherals could interact with them using their base address and high address. If, for example, you connected a MicroBlazeⁱ processor to the same bus as these three peripherals then it could read and write BRAMⁱ memory starting at the address 0x00000000 and ending at 0x00001FFF. Similarly it could use the serial port peripheral (RS232 UART) by reading and writing to the memory range 0x41000000 to 0x4100FFFF. You should take note that memory mapped address ranges apply to a single bus. If you design makes use of multiple independent buses then you will have multiple independent address maps. On a similar note, microprocessors can only interact with peripherals which appear some where in their memory map and thus can only interact with cores which are attached to the same bus at it is.

Project Tab

On the left of the main window in the section named the Project Information Area you should notice three tabs, the first of which is the Project tab. In this tab you will see all project files, options, and reference files associated with your system-on-chipⁱ design. The most important files here are the MHS, MSS, and UCF files. The MHS file, called system.mhs by default, is a textual representation of the same design information show in the system assembly views. It contains information about all of the soft-IP cores in the design along with the connections between the cores. The MSS file, called system.mss by default, is a textual representation of the information available in the Software Platform Settings menu option. This file contains a list of all software drivers associated with the soft-IP cores. These drivers are C libraries provided by Xilinxⁱ which help system-on-chipⁱ programmers interact with peripherals. The UCF file, called system.ucf by default, is the user constraints file. This file provides information about how to place nets during the synthesis process. Nets which go off-chip must be connected to specific I/O pins on the FPGAⁱ, the UCF file provides information about which nets are associated with which I/O pins and a couple of other things.

IP Catalog Tab

The IP Catalog tab shows a list of all soft-IP cores which are available for use in your system-on-chipⁱ design. IP Cores in this list are, by default, grouped into categories by their function. You can browse through the list to see what IP cores are available and double clicking on an IP core will add it to your system-on-chipⁱ design. Adding a new IP core does not connect it to any buses or any other peripherals. You will need to use the Bus Interface, Ports, and Addresses views described above to connect the new IP core to your system an make it available in a memory map.

Applications Tab

The last tab in the Project Information Area is the Applications tab. This tab shows all of the software applications which are available for use in your system-on-chipⁱ design. Multiple software applications can exist for any given system-on-chipⁱ design, although only a single application can be used to initialize any given BRAMⁱ in your system. You can select which application to use by right clicking on an application and choosing Mark to Initialize BRAMⁱ. Note that you must deactivate the previously selected application when you do this. Initializing a single BRAMⁱ with multiple different software applications will result in an error.

If you want to create a new software application then you can click on the Add Software Application Project entry. Each software application is associated with a single microprocessor in the design. Thus, designs which contain multiple microprocessors must contain multiple software applications, at least one software application per processor.